A. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, such as a vertical trench gate power IC, wherein a vertical trench gate semiconductor device and planar gate semiconductor device are formed on the same semiconductor substrate.
B. Description of the Related Art
A vertical semiconductor device (hereafter taken to be a trench gate MOS semiconductor device) in which a MOS gate (an insulated gate formed from a metal-oxide film-semiconductor) region is formed inside a trench has been proposed as a semiconductor device that realizes a reduction in on-state resistance and a reduction in area. A vertical semiconductor device is a device such that current flows from the front surface toward the rear surface, or from the rear surface toward the front surface, of a semiconductor substrate on which the device is formed. That is, it is a device in which current flows in the depth direction of the semiconductor substrate. Also, a semiconductor device (hereafter taken to be a vertical trench gate power IC) in which a vertical trench gate MOS semiconductor device is adopted as an output stage semiconductor device, and a control semiconductor device for controlling and protecting the output stage semiconductor device is formed aligned on the same semiconductor substrate, has been proposed as a vertical trench gate MOS semiconductor device that realizes increased reliability and increased destruction withstand at a low cost.
An example of a sectional configuration of main portions of a vertical trench gate power IC is shown in FIG. 6. FIG. 6 is a sectional view showing a configuration of a heretofore known vertical trench gate power IC. Vertical trench gate MOSFET (insulated gate field effect transistor) region 21 and lateral planar gate n-channel MOSFET region 22a are formed on the same semiconductor substrate in the vertical trench gate power IC. Vertical trench gate MOSFET region 21 is an active region of a vertical trench gate MOS semiconductor device, which is an output stage semiconductor device. Lateral planar gate n-channel MOSFET region 22a is a low breakdown voltage region in which is formed a lateral planar gate n-channel MOS semiconductor device, which is a control semiconductor device. Junction termination region 23 is formed in an outer peripheral portion enclosing vertical trench gate MOSFET region 21 and lateral planar gate n-channel MOSFET region 22a. Junction termination region 23 includes a field plate (metal wire 12f and polysilicon wire 6c) that alleviates electric field concentration that is liable to lead to breakdown at a low voltage.
The vertical trench gate power IC needs to have a relationship in which the gate threshold voltage of the MOSFET (hereafter referred to as the output stage MOSFET) formed as the output stage semiconductor device in vertical trench gate MOSFET region 21 is higher than the gate threshold voltage of the MOSFET (hereafter referred to as the control MOSFET) formed as the control semiconductor device in lateral planar gate n-channel MOSFET region 22a. The reason for this is to enable a protective function of the control MOSFET with respect to the output stage MOSFET. A description will be given, using vertical trench gate power IC 101 shown in the circuit block diagram of FIG. 7, of the necessity for this heretofore described relationship between the gate threshold voltage of the output stage MOSFET and the gate threshold voltage of the control MOSFET.
FIG. 7 is a circuit block diagram showing a configuration of a vertical trench gate power IC. Vertical trench gate power IC 101 is formed of output stage MOSFET 102 and control circuit unit 103. Control circuit unit 103 includes pull-down MOSFET (a control MOSFET) 107 and pull-down MOSFET 107 drive circuit 108. Normally, drive circuit 108 is configured of a MOSFET having the same characteristics as pull-down MOSFET 107. Also, the configuration is such that, as gate input terminal 104 of output stage MOSFET 102 and a power source terminal of control circuit unit 103 are in common, control circuit unit 103 operates with the input from gate input terminal 104 as power source voltage.
Typical functions of control circuit unit 103 include a function of protecting output stage MOSFET 102. That is, when an abnormal condition of output stage MOSFET 102, such as an overheat condition or overcurrent condition, is detected, control circuit unit 103 has a function of reducing the gate voltage of output stage MOSFET 102 to a ground potential by putting pull-down MOSFET 107 into an on-state, thereby cutting off the output current of output stage MOSFET 102 and preventing device destruction. In the circuit block of FIG. 7, reference sign 105 is a drain terminal, while reference sign 106 is a source terminal.
The relationship by which the gate threshold voltage of output stage MOSFET 102 is higher than the gate threshold voltage of the control MOSFET (pull-down MOSFET 107) is an effective means of solving the following problem. Hereafter, a description will be given regarding this point. The circuit configuration of the circuit block shown in FIG. 7 is such that, when the gate input voltage falls to or below the gate threshold voltage of pull-down MOSFET 107, pull-down MOSFET 107 stops operating. Because of this, by fixing (pulling down) the gate of output stage MOSFET 102 to the ground potential, it is no longer possible to cut off the current.
Also, as drive circuit 108 is also configured of a MOSFET having the same characteristics as pull-down MOSFET 107, drive circuit 108 stops operating, in the same way as pull-down MOSFET 107, and the function of cutting off the current to output stage MOSFET 102 is disabled. Because of this, the gate input voltage is applied to the gate of output stage MOSFET 102 in a condition in which the protective function of control circuit unit 103 is disabled. In the event that the gate threshold voltage of output stage MOSFET 102 is lower than the gate input voltage at this time, output stage MOSFET 102 is maintained in an on-state. In the event that the vertical trench gate power IC falls into an abnormal condition under these kinds of condition, the protective function is not enabled, and the possibility of device destruction increases.
Meanwhile, provided that the relationship in which the gate threshold voltage of output stage MOSFET 102 is higher than the gate threshold voltage of the control MOSFET is established, then even when the gate input voltage to the control MOSFET drops to the extent that the protective function is disabled, the gate input voltage to output stage MOSFET 102 also simultaneously falls to or below the gate threshold voltage of output stage MOSFET 102. Consequently, as output stage MOSFET 102 is maintained in an off-state, and the output current of output stage MOSFET 102 is cut off, it is possible to avoid device destruction caused by an abnormal output current.
Next, a description will be given of a problem when a CMOS (Complementary Metal Oxide Semiconductor) is adopted as the control MOSFET. Adopting a CMOS as the control MOSFET is useful in improving the performance of the control circuit unit 103, such as by reducing circuit current consumption. When configuring control circuit unit 103 with a CMOS, the minimum operating power source voltage of the drive circuit 108 is higher than when adopting a circuit configuration of only a lateral n-channel MOSFET as control circuit unit 103.
However, when adopting a CMOS as the control MOSFET, the following kind of problem occurs. When the gate input voltage falls to or below the gate threshold voltage of the control MOSFET, as heretofore described, it is necessary to provide vertical trench gate power IC 101 with a function whereby drive circuit 108 is prevented from stopping operating before output stage MOSFET 102. When adopting a CMOS as the control MOSFET, a lateral n-channel MOSFET and lateral p-channel MOSFET are provided as the control MOSFET. Because of this, in addition to the gate threshold voltage of the lateral n-channel MOSFET, it is necessary that the gate threshold voltage (absolute value) of the lateral p-channel MOSFET also falls to or below the gate threshold voltage of output stage MOSFET 102.
The following two methods are known as methods of realizing a desirable relationship between the gate threshold voltages of the output stage MOSFET and control MOSFET (CMOS) in the heretofore described kind of vertical trench gate power IC by adapting the chip manufacturing process.
The first method is a method whereby the gate threshold voltage of the control MOSFET is reduced by forming a diffusion layer having a conductivity type the opposite of that of a well region, at a concentration lower than that of the well region, in a layer below a gate electrode of the control MOSFET. However, the first method is such that it is necessary to add a step of carrying out an ion implantation of a low dose of a dopant of a conductivity type the opposite of that of the well region in order to form the diffusion layer having a conductivity type the opposite of that of the well region in the layer below the gate electrode of the control MOSFET. That is, an ion implantation step for adjusting the gate threshold voltage of the control MOSFET is added.
According to the first method, as the surface concentration of a control MOSFET channel formation region decreases, and a control MOSFET channel can easily be formed at a low gate voltage, it is possible to reduce the gate threshold voltage of the control MOSFET. Consequently, by selecting appropriate ion implantation conditions such that the gate threshold voltage of the control MOSFET falls to or below the gate threshold voltage of the output stage MOSFET, it is possible to realize the previously described desirable relationship between the gate threshold voltages of the output stage MOSFET and control MOSFET. However, the first method is such that it is necessary to selectively carry out the previously described gate threshold voltage adjusting ion implantation for each of the lateral n-channel MOSFET and lateral p-channel MOSFET configuring the CMOS. Consequently, there is a problem in that the number of steps increases, and the cost rises.
The second method is a method whereby the gate threshold voltage of the control MOSFET is reduced by a second gate oxide film of the control MOSFET being thinner than a first gate oxide film of the output stage MOSFET so that the control MOSFET channel is easily formed at a lower voltage. According to the second method, it is possible to simultaneously lower the gate threshold voltage of each of the lateral n-channel MOSFET and lateral p-channel MOSFET simply by carrying out the one step of forming the thin second gate oxide film of the control MOSFET. From this aspect, the second method is preferable to the first method.
As the desirable relationship between the gate threshold voltages of the output stage MOSFET and control MOSFET, that is, the relationship by which the gate threshold voltage of the output stage MOSFET is higher than the gate threshold voltage of the control MOSFET, is established in a vertical trench gate power IC in which a CMOS is adopted as the control circuit unit, as heretofore described, it is preferable that the second method is employed.
The following method has been proposed with regard to a method of manufacturing this kind of vertical trench gate power IC. Firstly, an isolation region is formed of a LOCOS oxide film (selective oxide film) on the front surface of a semiconductor substrate. Next, a trench is formed, and an output stage MOSFET trench gate structure is formed by a polysilicon film formation and an etching back of the polysilicon film being carried out sequentially. Next, after well regions configuring a lateral n-channel MOSFET and lateral p-channel MOSFET of a CMOS are formed on the front surface of the semiconductor substrate, a control MOSFET CMOS gate structure is formed by a thermal oxidation and polysilicon film formation being carried out sequentially (for example, refer to PTL 1 and 2 described below).
Also, with regard to a method of manufacturing the previously described kind of vertical trench gate power IC, there has been proposed a method in which, after a trench is formed in a semiconductor substrate, an oxide film is formed along the internal wall of the trench, and the oxide film above the CMOS region is removed with the resist covering the trench as a mask (for example, refer to PTL 3 described below).
However, when manufacturing a semiconductor device including a plurality of semiconductor devices, like the vertical trench gate power IC, using the second method for realizing the desirable relationship between the gate threshold voltages of the output stage MOSFET and control MOSFET of the vertical trench gate power IC in the manufacturing process, a LOCOS oxide film (selective oxide film) necessary for device isolation is formed, because of which the kinds of problem described below occur. Although there is little increase in the thickness of the LOCOS oxide film even after passing through a gate oxide film formation step, the LOCOS oxide film has a property such that the etching speed of the LOCOS oxide film is no different from the etching speed of the gate oxide film. Because of this, the thickness of the LOCOS oxide film decreases every time the gate oxide film formation and pattern-etching are repeated.
The decrease in the thickness of the LOCOS oxide film leads to a drop in the gate threshold voltage of an inter-device parasitic field MOSFET. As a result of this, an inversion layer is liable to be formed below the LOCOS oxide film in a device isolation region due to the potential of a metal electrode film and polysilicon wire disposed on the LOCOS oxide film, causing adverse effects such as a drop in inter-device isolation capability. Furthermore, as the LOCOS oxide film formed in the control lateral planar gate MOSFET region also has a function of alleviating electrical field concentration, thereby maintaining breakdown voltage, there is a problem in that the breakdown voltage drops due to the decrease in the thickness of the LOCOS oxide film. Consequently, taking the decrease in the thickness of the LOCOS oxide film into account, it is necessary to form the LOCOS oxide film in the device isolation region to a thickness greater than the desired thickness in advance. This is not desirable when considering the aspects of production throughput and cost.
Furthermore, the second method has the processing problems described below. Of the manufacturing steps, a step of partially removing only the control MOSFET portions of the gate oxide film formed over the whole of the front surface of the semiconductor substrate is such that the gate oxide film on the internal wall of the trench is covered with the resist in a condition in which the trench is opened (a condition in which nothing is embedded inside), and a photolithography step of removing the gate oxide film formed on the front surface of the semiconductor substrate is carried out with the resist as a mask. Because of this, the resist enters into the narrow, deep trench, and a problem occurs in that exposure of the resist that has entered to the bottom portion of the trench, and removal of the resist, is difficult. The further processing accuracy increases, and the narrower the trench becomes, the more pronounced and serious the problem becomes. Also, it is also difficult to clean sufficiently inside the trench in a subsequently carried out cleaning step, and there is concern that trench gate reliability will decrease due to the adherence of foreign objects, or the like.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.